1. Field of the Invention
The present invention relates to an integrated DRAM semiconductor memory and a method for operating the same.
2. Background Information
In a read cycle for integrated semiconductor memories, such as dynamic memory modules (DRAMs), in order to transport the evaluated bit line levels to the chip output, the bit line signals spread by a primary sense amplifier are switched onto local data lines (LDQs) via CSL switches in a first stage. For power-saving reasons, and in order that the primary sense amplifier that spreads the bit lines BL can drive the bit line signals within a short time on the LDQ, the capacitance of the LDQs that is to be subjected to charge reversal is usually reduced by segmentation or division of the same.
FIG. 1 shows a section of a cell array of a conventional DRAM memory with two cell blocks 20, 21. Situated between the two cell blocks is a SA strip 22, in which the above-mentioned primary sense amplifiers (SA) 1, the CSL switches 3, the segmented local data lines LDQT, LDQC and MDQ switches 5 are arranged. Three LDQ segments, designated by I, II and III are illustrated by way of example in FIG. 1. Complementary bit lines BLT, BLC, which run in each cell block 20, 21 in the row direction X, are connected to the primary SAs 1. Each SA outputs the bit line potentials to the local data lines LDQT and LDQC in the event of driving of the assigned CSL switch 3 by a CSL control signal, generated by a CSL driver 4, during a read operation. At this point in time, the local data lines LDQT, LDQC have already been connected by the MDQ switch 5 to an associated main data line MDQT, MDQC, which is in turn connected to a secondary sense amplifier (SSA) 2.
Consequently, a plurality of LDQ segments I, II and III are formed along a word line in each cell block 20, 21 which word line runs in the column direction Y and is not shown in FIG. 1 and the local data lines LDQT, LDQC thus segmented are connected at times, that is to say during a read cycle and a write cycle, via the MDQ switches 5 to a main data line MDQT, MDQC common to all the local data lines of an LDQ segment, and via said main data line to the SSA 2. It should be mentioned that the bit lines BLT, BLC, the primary sense amplifiers 1, the CSL switches 3, the local data lines LDQT, LDQC, the MDQ switches 5 and the main data lines MDQT, MDQC are set up for carrying or switching through differential or complementary data signals.
FIG. 3A shows a temporal sequence of a typical write-read cycle on the basis of the potentials on the connected main data lines MDQT, MDQC and local data lines LDQT, LDQC. During writing, the SSA 2 spreads the MDQ/LDQ lines to the full bit line level Vblh and, by means of a short pulsed CSL signal, the potentials are written to the bit lines BLT, BLC, the SA 1 being overwritten (toggled) under certain circumstances. Immediately after the end of the CSL pulse signal, the precharge of the MDQ/LDQ lines is begun, in order to find the MDQ/LDQ lines at the same potential in the event of a read command as a result of a renewed CSL pulse signal in the same LDQ segment. This precharge operation is carried out by an equalize (EQL) control circuit 6 arranged at the secondary sense amplifier 2 in the chip belt, in response to a precharge control signal 13. The precharge level is not a center level but rather the full bit line level Vblh on the true and complementary lines MDQT, MDQC and LDQT, LDQC.
FIG. 3A reveals that a shortening of the external cycle time or an increase in the cycle frequency during the transmission of the write-read commands is tantamount to a shortening of the precharge time tprecharge, since the length of the CSL pulse signal remains constant. By virtue of input-high-impedance contacts driven by the process technology within the MDQ switches 5, the precharge carried out on the main data lines MDQT, MDQC can have an effect on the local data lines LDQT, LDQC only in a time-delayed manner. However, assuming inverted (logical) data between write and read commands, this can have the effect that the signal on the bit line BLT, BLC that is switched on to the local data lines LDQT and LDQC during the read operation by the primary sense amplifier 1 via the CSL switch 3 is not strong enough to generate a sufficient differential signal on the complementary local data lines LDQT, LDQC. This can lead to an incorrect evaluation of the secondary sense amplifier.
In the worst case, the complementary local data lines LDQT, LDQC are still fully spread (a precharge could not yet take place) when the CSL pulse signal of the read command arrives. Analogously to a write command, this leads to the toggling of the SA 1 and thus to the writing back of the incorrect data information. What is problematic in this case is primarily the fact that only one MDQ switch 5 is used per LDQ segment in order to switch through the LDQ precharge. This results in a high susceptibility which causes the semiconductor memory module to fail beyond the repair limit.
DE 196 32 780 A1 (see, in particular, FIG. 3 with description) discloses a semiconductor memory in which, in order to accelerate a precharge operation, which is called “restore” in this document, at least two of the bit line pairs are connected via the bit line switches that are present anyway.